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| Technical Program—Advance Program |
Monday | Tuesday | Wednesday
Monday AM, June 23, 2008
Location: TBA |
Plenary Session
Session Organizer: Joerg Appenzeller
Session Chair: Steve Koester |
| 8:50 AM |
Welcoming Remarks
Presentations: IEEE Fellows and Best Student Paper Awards |
| 9:10 AM |
I.-1 Plenary Paper
40 Years of Heterojunctions: No End in Sight
Jerry M. Woodall, Purdue University, ECE Department, West Lafayette, Indiana, USA
|
| 10:00 AM |
Break |
| 10:20 AM |
I.-2 Plenary Paper
Scaling, Power, and the Future of CMOS Technology
Mark Horowitz, Stanford University, Department of Electrical Engineering, Palo Alto, California, USA
|
| 11:10 AM |
I.-3 Plenary Paper
Toward Carbon Based Electronics
Philip Kim, Department of Physics, Columbia University, New York , New York, USA
|
Monday PM, June 23, 2008
Location: TBA |
Session II.A.
Nano I - CNTs and Graphene
Session Organizer: Zhihong Chen
Session Chair:TBA |
| 1:30 PM |
II.A-1 Invited Paper
High Performance Carbon Nanotube RF Electronics
H. Zhang, J. A. Payne, A. A. Pesetski, J. E. Baumgardner, W. Miller, K. Krishnaswamy, A. Jazairy, J. X. Przybysz, and J. D. Adam, Northrop Grumman Electronics Systems, Linthicum, Maryland, USA
|
| 2:10 PM |
II.A-2
High-Performance Carbon Nanotube Field-Effect Transistors Using Low-Energy Ion Implantation
K. Maehashi1, K. Nishiguchi1, Y. Ohno1, K. Inoue1, K. Yamamoto2, and K. Matsumoto1, 1The Institute of Scientific and Industrial Research, Osaka University, Ibaraki, Osaka, JAPAN and 2National Institute of Advanced Industrial Science and Technology,
Higashi, Tsukuba, Ibaraki, JAPAN
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| 2:30 PM |
II.A-3
Impact Ionization in Semiconducting Single Wall Carbon Nanotubes
A. Liao and E. Pop, Dept. of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, Micro and Nanotechnology Lab, Urbana Illinois, USA
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| 2:50 PM |
II.A-4
Convertible Transistor between Resonant Tunneling Transistor and Single Hole Transistor Using Single-Walled Carbon Nanotube
T. Kamimura1,2, Y. Ohno3, and K. Matsumoto1,3, 1AIST, Tsukuba, Ibaraki, JAPAN, 2JSPS, and 3Osaka Univ. ISIR, Osaka, JAPAN
|
| 3:10 PM |
Break |
| 3:30 PM |
II.A-5
Flexible and Wearable Devices based on Transferred Aligned Carbon Nanotube Arrays
K. Ryu, A. Badmaev, and C. Zhou, Dept. of Electrical Engineering, University of Southern California, Los Angeles, California, USA
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| 4:10 PM |
II.A-6
Theory of Multi-tube Carbon Nanotube Transistors for High Speed Variation-Tolerant Circuits
A. Raychowdhury1, J. Kurtin1, S. Borkar1, V. De1, K. Roy2, and A. Keshavarzi1,1Circuit Research Labs, Intel Corporation, Hillsboro, Oregon, USA and 2Purdue University, West Lafayette, Indiana, USA
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| 4:30 PM |
II.A-7
Epitaxial graphene transistors on SiC substrates
J. Kedzierski, P.-L. Hsu, P. Healey, P. Wyatt, and C. Keast, MIT Lincoln Laboratory, Lexington, Massachusetts, USA
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| 4:50 PM |
II.A-8
Chemical Doping of Graphene Nanoribbon Field-Effect Devices
Y.-M. Lin1, D. B. Farmer1, G. S. Tulevski1, S. Xu2, R. G. Gordon2, and P. Avouris1, 1IBM T. J. Watson Research Center, Yorktown Heights, New York, USA and 2Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, USA
|
| 5:10 PM |
II.A-9
Current-carrying Capacity of Long & Short Channel 2D Graphene Transistors
X. Luo, Y. Lee, A. Konar, T. Fang, H. Xing, G. Snider, and D. Jena, Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, USA
|
Monday PM, June 23, 2008
Location: TBA |
Session II.B. Alternative CMOS Devices
Session Organizers: Judy Hoyt, Aaron Thean
Session Chairman: Wilman Tsai, David Fried |
| 1:30 PM |
II.B-1 Invited Paper
Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?
Suman Datta, Department of Electrical Engineering, Pennsylvania State University, University Park, Pennsylvania, USA
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| 2:10 PM |
II.B-2
High-performance Inversion-type E-mode In0.65Ga0.35As MOSFETs with ALD HfO2 as Gate Dielectric
Y. Xuan1, T. Shen2, Y. Q. Wu1, M. Xu1, and P. D. Ye1, 1School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, USA and 2Department of Physics, Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana, USA
|
| 2:30 PM |
II.B-3
Self-aligned inversion-channel and D-mode InGaAs MOSFET using Al2O3/Ga2O3(Gd2O3) as gate dielectrics
T. D. Lin1, C. P. Chen1, H. C. Chiu1, P. Chang1, C. A. Lin2, M. Hong1, J. Kwo2, and W. Tsaic3, 1Department of Materials Sci. and Eng., 2Department of Physics, National Tsing Hua University, Hsinchu, TAIWAN and 3Intel Corporation, Santa Clara, California, USA
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| 2:50 PM |
II.B-4
High Performance Long- and Short-Channel In0.7Ga0.3As-channel MOSFETs
Y. Sun, E. W. Kiewra, J. P. de Souza, J. J. Bucchignano, K. E. Fogel, D. K. Sadana and G. G. Shahidi,
IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA
|
| 3:10 PM |
Break |
| 3:30 PM |
II.B-5
High Electron Mobility (2270 cm2/Vsec) In0.53Ga0.47As Inversion Channel NMOSFETs
with ALD ZrO2 Gate Oxide Providing 1 nm EOT
S. Koveshnikov1,4, N. Goel1,2, P. Majhi1,2, C. K. Gaspe3, M. B. Santos3, S. Oktyabrsky4, V. Tokranov4, M. Yakimov4, R. Kambhampat4, H. Bakhru4, F. Zhu5, J. Lee5, and W. Tsai1, 1Intel Corporation, Santa Clara, CA, USA, 2SEMATECH, Austin, Texas, USA, 3The University of Oklahoma, Norman, Oklahoma, USA, 4University at Albany-SUNY,Albany, New York, USA, and 5University of Texas at Austin, Austin, Texas, USA
|
| 4:10 PM |
II.B-6
DC and RF Characterization of Sub-100-nm-Gate-Length Strained Ge-on-Insulator p-MOSFETs
S. W. Bedell1, A. Majumdar1, K. A. Jenkins1, J. A. Ott1, J. Arnold2, K. Fogel1, S. J. Koester1, and D. K. Sadana1, 1IBM T. J. Watson Research Center, Yorktown Heights, New York, USA and 2IBM Research Division, Albany Nanotech, Albany, New York, USA
|
| 4:30 PM |
II.B-7
Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications
S. Mookerjea and S. Datta, Department of Electrical Engineering, Pennsylvania State University, University Park, Pennsylvania, USA
|
| 4:50 PM |
II.B-8
Late News
|
| 5:10 PM |
II.B-9
Late News
|
Monday PM, June 23, 2008
7:00 PM-9:00 PM
Location: TBA |
Session III. Poster Session
Session Organizer: Takatomo Enoki |
|
III-1 Student Paper
Vertical Flash memory devices with Protein-assembled Nanocrystal floating gate
and Al2O3 control oxide
F. Ferdousi, J. Sarkar, S. Tang, D. Shahrjerdi, T. Akyol, J. P. Donnelly, E. Tutuc, S. K. Banerjee, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, USA
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III-2
A Nonvolatile Memory Operation by Ferroelectric Modulation of Interface Conductance in a Combinatorial Oxide Structure
Y. Kaneko, H. Tanaka, Y. Kato, and Y. Shimada, Semiconductor Device Research Center, Matsushita Electric Industrial Co., Ltd., Nagaokakyo City, Kyoto, JAPAN
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III-3 Student Paper
Improved 150oC Retention in Hf0.3O0.5N0.2 Memory Device with Low Voltage and Fast Writing
S. H. Lin1, H. J. Yang2, H. L. Kao3, F. S. Yeh1, and Albert Chin2, 1E.E. Dept., Nat. Tsing Hua Univ., 2E.E. Dept., Nat. Chiao-Tung Univ., Hsinchu, TAIWAN ROC, and 3Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, TAIWAN, ROC
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III-4 Student Paper
Multi-bit functional NOR type SONOS memories
Moonkyung Kim1, Chung Woo Kim2, Jo-won Lee3 and S. Tiwari1, 1Department of Electrical and Computer Engineering Cornell University, Ithaca, New York, USA, 2Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., Kiheung, Kyunggi, KOREA, and 3National Program for Tera-level Nano Devices, Seoul, KOREA
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III-5 Student Paper
Structural Sensitivity of Interband Tunnel Diodes for SRAM
S. Sutar, Q. Zhang, and A. Seabaugh, University of Notre Dame Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, USA
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III-6 Student Paper
Performance Evaluation of III-V Double-Gate n-MOSFETs
D. Kim1, T. Krishnamohan1,2, K. C. Saraswat1, 1Department of Electrical Engineering, Stanford University, Stanford, California, USA, and 2Intel Corporation, USA
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III-7
Energy-Reversible Complementary NEM Logic Gates
K. Akarvardar, D. Elata, R. T. Howe, H.-S. P. Wong, Center for Integrated Systems, Stanford University, Stanford California, USA
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III-8 Student Paper
Gate-First Low Vt Al/TaN/Ir/HfLaO p-MOSFET Using Simple Laser Annealing
N. C. Su1, C. H. Wu1, M. F. Chang2, J. Z. Huang3, S. J. Wang1, W. C. Lee1, P. T. Lee2, H. L. Kao4 and Albert Chinc5, 1Inst. of Microelectronics, Dept. of EE, National Cheng Kung University, Tainan, TAIWAN, ROC, 2Dept. of Photonic and Inst. of Electro-Optical Eng., National Chiao-Tung University, Hsinchu, TAIWAN, ROC, 3Dept. of Electronics Eng., National Chiao-Tung University, Hsinchu, TAIWAN, ROC, 4Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, TAIWAN, ROC, and 5Nano-Electronics Consortium of Taiwan
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III-9 Student Paper
Can the Interband Tunnel FET Outperform Si CMOS?
Q. Zhang and A. Seabaugh, Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, USA
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III-10 Student Paper
BTBT Transistor Scaling: Can they be Competitive with MOSFETs?
R. Woo, H.-Y. S. Koh, C. Onal, P.B. Griffin, and J. D. Plummer, Stanford University Center for Integrated Systems, Stanford, California, USA
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III-11 Student Paper
Optimization of n-channel tunnel FET for the sub-22nm gate length regime
V. Nikam1, K. K. Bhuwalka2 and A. Kottantharayil1, 1Department of Electrical Engineering, IIT Bombay, Mumbai, INDIA and 2Univ. der Bundeswehr Munich presently at ADTD, TSMC, Hsinchu, TAIWAN, R.O.C.
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III-12
Improving the performance of band-to-band tunneling transistors by tuning the gate oxide and the dopant concentration
C. Sandow1, J. Knoch2, C. Urban1, S. Mantl1, 1Forschungszentrum, Juelich, GERMANY and 2IBM Research GmbH, Zurich Research Laboratory, Rüschlikon, SWITZERLAND
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III-13 Student Paper
Inversion n-channel GaN MOSFETs with atomic-layer-deposited Al2O3 as gate dielectrics
Y. C. Chang1, W. H. Chang1, H. C. Chiu1, K. H. Shiu1, C. H. Lee1, M. Hong1, J. Kwo2, J. M. Hong3 and C. C. Tsai3, 1Department of Materials Science and Eng., National Tsing Hua University, Hsinchu, TAIWAN, R.O.C, 2Department of Physics, National Tsing Hua University, Hsinchu, TAIWAN, R.O.C., and 3HUGA optotech Inc.,Taichung, TAIWAN, R.O.C.
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III-14
Self-Aligned Low-Schottky Barrier Deposited Metal S/D MOSFETs with Si3N4M/Si Passivation
D. Connelly1, P. Clifton1, C. Faulkner1, J. Owens2, and J. Wetzel2, 1Acorn Technologies, Palo Alto, California, USA and 2ATDF, Austin, Texas, USA
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III-15 Student Paper
The Mechanism of the Negative Vfb Shift by Capping a Thin Layer of Me2O3 (Me=Gd, Y or Dy)
M. Zhang, F. Zhu, H.-s. Kim, H. Zhao, I. Ok and J. C. Lee, Department of Electrical and Computer Engineering, the University of Texas, Austin, Texas, USA
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III-16 Student Paper
High Quality Interfacial Layer using High-Density Plasma Oxidation in Germanium High-κ Gate stack
G. Thareja1, M. Kobayashi1, Y. Oshima2, James McVittie1, Peter Griffin1 and Yoshio Nishi1, 1Department of Electrical Engineering, Stanford University, Stanford, California, USA and 2Material Science and Engineering, Stanford University, Stanford, California, USA
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III-17 Student Paper
Fermi-Level Depinning of GaAs for Ohmic Contacts
J. Hu, D. Choi, J. S. Harris, K. Saraswat, H.-S. P. Wong, Department of Electrical Engineering, Stanford University, Stanford, California, USA
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III-18 Student Paper
Self-Aligned n-channel MOSFET on InP and In0.53Ga0.47As Using Physical Vapor Deposition HfO2 and Silicon Interface Passivation Layer
InJo Ok1, H. Kim1, M. Zhang1, F. Zhu1, H. Zhao1, S. Park1, J. Yum1, Domingo Garcia2, Prashant Majhi2, N. Goel3, W. Tsai3, C.K. Gaspe4, M.B. Santos4, and J. C. Lee1, 1Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas, Austin, TX, USA, 2SEMATECH, Austin, Texas, USA, 3Intel Corporation, Santa Clara, California, and 4The University of Oklahoma, Norman, Oklahoma, USA
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III-19
Subthreshold Characteristics of High-performance Inversion-type Enhancement-mode InGaAs NMOSFETs with ALD Al2O3 as Gate Dielectric
P.D. Ye1, Y. Xuan1, Y.Q. Wu1, T. Shen1, H. Pal1, D. Varghese1, M.A. Alam1, M.S. Lundstrom1, W.K. Wang2, J.C.M. Hwang2, and D. A. Antoniadis3, 1School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana, USA, 2Department of Electrical Engineering, Lehigh University, Bethlehem, Pennsylvania, USA, and 3Department of Electrical Engineering and Computer Science, MIT, Cambridge, Massachusetts, USA
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III-20
OH dangling-bond saturation and dielectric function effects in ultra-scaled SNW-FETs
E. Gnani1, S. Reggiani1, A. Gnudi1, R. Colle2 and G. Baccarani1, 1ARCES and DEIS, University of Bologna, Bologna, ITALY and 2Dipartimento di Chimica Applicata e Scienza dei Materiali, University of Bologna, Bologna, ITALY
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III-21 Student Paper
Size Dependent Thermal Activation Study of Single InSb Nanowire Devices for High Speed and Low Power Digital Logic Applications
M. I. Khan1, M. Penchev2, R. Lake2, M. Ozkan2, C. S. Ozkan1, 1Department of Mechanical Engineering and 2Department of Electrical Engineering, University of California, Riverside, California, USA
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III-22 Student Paper
Performance Analysis of Germanium Nanowire Tunneling Field Effect Transistors
N. Jain, E. Tutuc, S. K. Banerjee, and L. F. Register, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, USA
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III-23 Student Paper
Nanoscale thermoelectric power generation FinFETs
E.A. Hoffmann1, H.A. Nilsson2, N. Nakpathomkun1, A.I. Persson1, L. Samuelson2, H. Linke1, 1Physics Department and Materials Science Institute, University of Oregon, Eugene, Oregon, USA and 2Solid State Physics/The Nanometer Structure Consortium, Lund University, Lund, SWEDEN
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III-24 Student Paper
Anodization process of aluminum microelectrode for a single-electron transistor operating at room temperature
T. Muto, Y. Kimura and M. Niwano, Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, Aoba-ku, Sendai, JAPAN
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III-25 Student Paper
Hierarchical modeling of carbon nanoribbon devices for CNR-FETs engineering
R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Cinacchi and G. Baccarani, ARCES and DEIS, University of Bologna, Bologna, ITALY
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III-26
Electronic Structure and Carrier Transport in Thin Graphene Films under a Vertical Electric Field Based on Ab-initio Calculations
M. Ohtuchi, N. Harada, M. Ito and Y. Awano, Fujitsu Laboratories Ltd., Nanotechnology Research Center, Atsugi, JAPAN
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III-27 Student Paper
Threshold Voltage and 1/f Noise Degradation in Carbon Nanotube Field Effect Transistors under Hot-Carrier Stress
P. Lim1, X. Wang2, H. Dai3, Y. Nishi1, and J. Harris1, 1Center for Integrated Systems, Stanford University, Stanford, California, USA, 2Department of Physics, Stanford University, Stanford, California, USA, and 3Department of Chemistry, Stanford University, Stanford, California, USA
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III-28
Is there an Opportunity for Carbon Nanotube FETs in Very-High-Frequency Applications?
L. Chen and D. L. Pulfrey, Electrical and Computer Engineering Department, University of British Columbia, Vancouver, British Columbia , CANADA
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III-29 Student Paper
Aligned single-walled carbon nanotube thin-film transistor arrays for transparent electronics
S. H. Lin1, H. J. Yang2, H. L. Kao3, F. S. Yeh1, and Albert Chin2, 1E.E. Dept., Nat. Tsing Hua Univ., 2E.E. Dept., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ROC, and 3Dept. of Electronic Engineering, Chang Gung Univ., Tao-Yuan, TAIWAN, ROC
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III-30
An Equivalent Circuit for Separable Electron Streams in a Gated Dirac Transmission Line
P. M. Solomon, IBM, SRDC, T.J. Watson Research Center, Yorktown Heights, New York, USA
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III-31 Student Paper
Analytical Degenerate Carrier Density and Quantum Capacitance for Semiconducting Carbon Nanotubes
D. Akinwande, J. Liang, and H.-S. P. Wong, Electrical Engineering, Stanford University, Stanford, California, USA
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III-32 Student Paper
Rapid and Label-Free Cell Detection by Metal-Cluster-Decorated Carbon Nanotube Biosensors
F. N. Ishikawa and C. Zhou, Department of Electrical Engineering, University of Southern California, Los Angeles, California, USA
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III-33
Voltage Compliant SOI MESFETs for High Linearity RF Front Ends
S. Wilk, A. Balijepalli, W. Lepkowski, J. Ervin and T. J. Thornton, Arizona State University, Center for Solid State Electronics Research, Tempe, Arizona, USA
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III-34
Scaling of High-Performance InAs/AlSb/GaSb Heterostructure Detectors for Millimeter-Wave and Submillimeter-Wave Sensing and Imaging
N. Su1,2, Z. Zhang1, R. Rajavel3, P. Deelman3, J. N. Schulman3,4, and P. Fay1, 1Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, USA, 2present address: IBM Semiconductor Research and Development, Hopewell Junction, New York, USA, 3HRL Laboratories LLC, Malibu, California, USA, and 4present address: The Aerospace Corp., El Segundo, California, USA
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III-35
GaN-based HFET Design for Ultra-high frequency Operation
A. Koudymov and M. Shur, Dept. of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, USA
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III-36
Temperature-dependent microwave noise characteristics of AlGaN/GaN HEMTs on silicon substrate
Z. H. Liu1,2, S. Arulkumaran1, G. I. Ng1,2, and T. Xu2, 1MMIC Design Center, Temasek Laboratories@NTU, Nanyang Technological University, SINGAPORE and 2School of EEE, Nanyang Technological University, SINGAPORE
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III-37
High-Performance E-Mode AlGaN/GaN HEMTs with LT-GaN Cap Layer Using Gate Recess Techniques
T. Adachi1, T.i Deguchi1, A. Nakagawa1, Y. Terada2, and T.i Egawa2, 1Advanced Technology Center, Research Laboratory, New Japan Radio Co., Ltd.,Fujimino, Saitama, JAPAN and 2Research Center for Nano-Device and System, Nagoya Institute of Technology, Nagoya, Aichi, JAPAN
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III-38
Surface Passivation of AlGaN/GaN HEMTs
S. Rajan, Y. Pei, Z. Cheng, S. P. DenBaars and U. K. Mishra, Electrical and Computer Engineering Department, University of California, Santa Barbara, California, USA |
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III-39
High-efficiency, high-breakdown AlGaN/GaN HEMTs with lifetimes beyond 20 years
P. Waltereit1, W. Bronner1, R. Quay1, M. Dammann1, S. Müller1, M. Mikulla1, F. van Rijs2, T. Rödle2, and K. Riepe3, 1Fraunhofer Institute for Applied Solid State Physics, Freiburg, GERMANY, 2NXP Semiconductors, Nijmegen, The Netherlands, and 3United Monolithic Semiconductors, Ulm, GERMANY
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III-40
Lasing characteristics of ZnO nanostructures with various morphologies
S. H. Lee1, J.-S. Ha1, H. Lee1, H. Lee1, H. Miyazaki2, T. Goto1, and T. Yao1, 1Center for Interdisciplinary Research and 2Department of Applied Physics, Tohoku University, Aramaki, Aoba-ku, Sendai, JAPAN
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III-41 Student Paper
Top-Bottom Stripe Thin Film InGaAs/GaAsP Laser integrated on Silicon
S. Palit2, G. Tsvid2, J. Kirch2, J. Y.-T. Huang2, T. Tyler1 S.-Y. Cho1, N. Jokerst1, L. Mawst2, and T. Kuech3, 1ECE Dept, Duke University, Durham, North Carolina, USA, and 2ECE Dept., University of Wisconsin, Madison, Wisconsin, USA and 3CBE Dept. University of Wisconsin, Madison, Wisconsin, USA
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III-42
The characteristics of chemical lift off method using metallic buffer layer and its application to the vertical light emitting diodes
S. W. Lee, J.-S. Ha, H. J. Lee, H.-J. Lee, S. H. Lee, T. Goto, K. Fujii, M. W .Cho, and T. Yao, Center for Interdisciplinary Research, Tohoku University, Aramaki, Aoba-ku, Sendai, JAPAN |
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III-43 Student Paper
Use of Highly Reflective Ohmic Contact and Surface KrF Laser Roughening to Improve Light Output of Vertical GaN-Based Light-Emitting Diodes
W.-C. Lee1, K.-M. Uang2, D.-M. Kuo1, J.-C.Chou1, T.-M. Chen2, H.-Y. Kuo1, and S.-J. Wang1, 1Institute of Microelectronics, Dept. of Electrical Eng., National Cheng Kung Univ., Tainan, TAIWAN and 2Dept. of Electrical Eng., WuFeng Institute of Technology, Chia-yi, TAIWAN
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III-44 Student Paper
Extremely Ultra-Shallow p+-n Boron-Deposited Silicon Diodes Applied to DUV Photodiodes
F. Sarubbi, L. K. Nanver, T. L. M. Scholtes, and S. N. Nihtianov, DIMES, Delft University of Technology, Delft, THE NETHERLANDS
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III-45
Light-response Characteristics of Organic Thin Film Transistors based on Triisopropylsilyl Pentacene
Y.-H. Kim1,2, S.-K. Park1, S.-G. Park2, M.-K. Han2, J.-I. Han1, 1Information Display Research Center, Korea Electronics Technology Institute, Seongnam, KOREA and 2School of Electrical Engineering and Computer Science, Seoul National University, Seoul, KOREA
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III-46 Student Paper
High-Speed, Low-Temperature Integrated ZnO/Organic CMOS Circuits
D. A. Mourey1,2, S. K. Park4, D. Zhao1,3, J. Sun1,3, Y. Li1,3, S. Subramanian5, S. F. Nelson4, D. H. Levy4, J. E. Anthony5, T. N. Jackson1,3, 1Center for Thin Film Devices and Materials Research Institute, Penn State University, University Park, Pennsylvania, USA, 2Department of Material Science Engineering, Penn State University, University Park, Pennsylvania, USA, 3Department of Electrical Engineering, Penn State University, University Park, Pennsylvania, USA, 4Eastman Kodak Company, Rochester, New York, USA, and 5Department of Chemistry, University of Kentucky, Lexington, Kentucky, USA
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III-47 Student Paper
Top-gated Thin Film FETs Fabricated from Arrays of Self-aligned Semiconducting Carbon Nanotubes
M. I. Engel1, J. P. Small1, M. Steiner1, Y.-M. Lin1, A. A. Green2, M. C. Hersam2, P. Avouris1, 1IBM Research Division, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA and 2Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois, USA
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III-48 Student Paper
Study of the Density of States of α-InGaZnO Using Field-Effect Technique
C. Chen1, T.C. Fung1, K. Abe2, H. Kumomi2 and J. Kanicki1, 1Dept. of Electrical Engineering and C
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III-49
An Ultra Wide Range MEMS Variable Capacitor with a Liquid Metal
S. S. Pottigari and J. W. Kwon, University of Missouri, Columbia, Missouri, USA
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III-50 Student Paper
Laterally vibrating-body double gate MOSFET with improved signal detection
D. Grogg, H.C. Tekin, N.D. Badila-Ciressan, M. Mazza, D. Tsamados, A.M. Ionescu
Laboratory of micro/nano-electronic devices, Ecole Polytechnique Fédérale de Lausanne, SWITZERLAND
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III-51
On-chip Micromechanical Parametric Resonator Based on the Piezoelectricity in GaAs/AlGaAs Modulation-Doped Heterostructure
I. Mahboob and H. Yamaguchi, NTT Basic Research Laboratories, NTT Corporation, Atsugi, Kanagawa, JAPAN
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III-52
Logic Devices with Spin Wave Buses: Potential Advantages and Shortcoming
A. Khitun1, M. Bao1, J.-Y. Kim1, A. Hong1, A. P. Jacob2, and K. L.Wang1, 1Department of Electrical Engineering, University of California, Los Angeles, California, USA, and 2Western Institute of Nanoelectronics (WIN) & TMG External Programs, Intel Corporation, Los Angeles, California, USA
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III-53
Key Role of Non Equilibrium Spin Density in Determining Spin Torque
S. Salahuddin, D. Datta and S. Datta, School of Electrical and Computer Engineering and NSF Network for Computational Nanotechnology, Purdue University, West Lafayette, Indiana, USA
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III-54
Suitability for Digital Logic and Scaling of Atomistic Magnetic QCA
D. E. Nikonov, G. I. Bourianoff, and P. A. Gargini, Technology Strategy, Technology and Manufacturing Group, Intel Corp., Santa Clara, California, USA
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III-55 Student Paper
A Spin-Capacitor with Paramagnetic Impurities Embedded in GaAs
D. Saha, D. Basu, and P. Bhattacharya, Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan, USA
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III-56 Student Paper
Observation of magnetoresistance polarity reversal in 3D to 2D tunneling in an asymmetric GaMnAs resonant tunneling diode
E. Likovich1, K. Russell1, W. Yi1, V. Narayanamurti1, K.-C. Ku2, M. Zhu2, and N. Samarth2, 1School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, USA and 2Physics Department, Penn State University, University Park, Pennsylvania, USA
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III-57
Coplanar waveguide radio frequency ferromagnetic parametric amplifier
M. Bao1, A. Khitun1, Y. Wu1, J.-Y. Lee1, A. P Jacob2, and K. L. Wang1, 1Department of Electrical Engineering, University of California, Los Angeles, California, USA and 2TMG External Programs, Intel Corporation, Los Angeles, California, USA
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